Physical implementation flow of a modern electronic design often starts with the floorplanning and placement stage at which various instances, blocks, cells, etc. are inserted in a layout canvas of the electronic design according to various criteria or rules governing the floorplan or the placement layout. This placement layout may then be forwarded to a router to perform, for example, global and detailed routing to complete the physical design. Conventional floorplanners or placement engines are merely concerned with the floorplanning or placement rules and constraints but are not aware of the routing or routability requirements, rules, or constraints or do not have sufficient knowledge therefor and thus may cause various issues or errors during the subsequent routing stage. Some errors may even require a portion of a layout be ripped up and rerouted.
For example, when inserting a block, a cell (e.g., an intellectual property or IP cell, a parameterized or non-parameterized cell, a custom cell, etc.), or a macro (collectively block hereinafter) into a layer of a floorplan or a placement layout, conventional floorplanner or placement tools merely consider the design rules, constraints, and/or requirements pertaining to the layer into which the block is to be inserted yet often fail to account for design rules, constraints, and/or requirements pertaining to neighboring layers. With the advanced technology nodes that permit only one routing direction for each layer, these conventional approaches often cause routability issues.
As a result, routing a modern electronic designs or routability of an electronic design may be severely affected by the placement of devices in the electronic design. For example, if a device is placed in a layout so that a pin in the device does not cover enough area of a routing track, a via may not be inserted to interconnect the pin with another pin on another layer of the electronic design.
Conventional approaches resolve these routability issues by using double vias. Double vias or redundant vias are often used to improve yield and reliability of electronic designs because when one of the double or redundant vias fails, the other via may nevertheless serve to maintain the functionality of the chip. In the aforementioned example of a pin not covering sufficient area for via insertion, the use of double or redundant vias may lose its advantages in enhancing reliability and yield because both vias are needed due to the pin's insufficient coverage of a routing track.
In addition to the additional costs in the implementation and the use of the invaluable real estate on silicon, double or redundant vias have been shown not to exhibit any advantages in terms of, for example, EM reliability. Also, double or redundant vias may cause the capacitance to increase, especially in deep sub-micron technology nodes, and may pose additional challenges in a timing analysis because the RC time constant is nearly doubled for a redundant via, especially for short connections.
Routability such as the aforementioned pin access has become one of the most difficult challenges for routing in advanced technology nodes (e.g., 14 nm and below) for which double-patterning lithography has to be used for manufacturing lower metal routing layers with tight pitches, such as M2 (metal two layer) and M3 (metal three layer). Some conventional approaches employ self-aligned double patterning (SADP) techniques that provide better control on line edge roughness and overlay, but the SADP techniques also impose highly restrictive design constraints as well as regular and structured layout patterns that greatly limit the flexibility in design options and hence the overall costs of the implementation of IC (integrated circuit) designs will increase.
Moreover, modern electronic design involving advanced technology nodes often require wires and interconnects be implemented within rows or on routing tracks or even on routing tracks of legal track patterns governed by the semiconductor fabrication foundries. In these modern electronic designs, vias cannot be added to route into or out of a pin when the pin is not placed at a location to cover a sufficient area of a routing track. It shall be noted that a routing track is merely an imaginary line or line segment derived from, for example, the manufacturing grids provided by semiconductor fabrication foundries. Therefore, a routing track has no width yet may be associated with a width value so that a wire may assume or inherit the associated width value when implemented along this routing track.
Therefore, there is a need for implementing routing aware placement for an electronic design to address at least the aforementioned shortfalls of conventional approaches.